In the applications of a power transistor, the overall dimension and heat dissipation are two important parameters of the device. The heat dissipation of the device is generally improved by exposing part of the electrode of the transistor, but the implementation process is very complicated. In switching circuits such as synchronous buck converters, half bridge converter and inverters, two power MOSFETs are switched in complementary fashion.
As shown in FIG. 1A, U.S. Pat. No. 7,485,954 discloses a stacked dual MOSFET package. The integrated circuit package includes a high side MOSFET die 230 coupled to a first conductive tab 210 such that a drain of the high side MOSFET die 230 is attached on and electrically connected to the first conductive tab 210; a second conductive tab 243 attached on and electrically connected to a source of the high side MOSFET die 230; and a low side MOSFET die 250 coupled to the second conductive tab 243 such that a drain of the low side MOSFET die 250 is attached on and electrically connected to the second conductive tab 243. The high side MOSFET die 230, the low side MOSFET die 250, the first conductive tab 210 and the second conductive tab 243 are stacked so that the second conductive tab 243 electrically contacts with a top electrode of the high side MOSFET die 230 and a bottom electrode of the low side MOSFET die 250, and the bottom surface 215 of the conductive tab 210 and the bottom surface 247 of the conductive tab 240 are coplanar.
Furthermore, as shown in FIG. 1B, U.S. Pat. No. 8,519,520 discloses a semiconductor device package with a high-side chip and a low-side chip and a manufacturing method thereof. In the device, the low-side chip 200 and the high-side chip 300p are attached to the two opposite sides of a lead frame respectively, so that a bottom drain electrode of the low-side chip 200 is electrically connected to a top side of a die paddle 110 and a top source electrode of the high-side chip 300p is electrically connected to a bottom side of the die paddle 110 through solder balls 311. A top gate electrode of the low-side chip 200 is connected to a pin 122 of the lead frame by a metal clip 230p and the top gate electrode of the high-side chip 300p are connected to a pin 123 of the lead frame, where the pins 122 and 123 are coplanar. In the invention, the stacking structure of the low-side chip 200, the die paddle 110 of a lead frame 100 and the high-side chip 300p reduces the package size. After encapsulating the low-side chip 200, the die paddle 110 of a lead frame 100 and the high-side chip 300p with a package body 400p, a metal layer 320 (or a conductive layer 320′) covering the back side of the high-side chip 300p is exposed outside of a package body 400p at the bottom surface of the semiconductor device to improve the heat dissipation of the device.
The prior art semiconductor device packages of FIG. 1A and FIG. 1B cannot provide the best heat dissipation and the device has a relatively large footprint, for example the size of a pin or a metal clip cause the device to occupy a large area on a PCB circuit board.
It is within this context that embodiments of the present invention arise.